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technical note general-purpose operational amplifier / comparator low voltage cmos comparator bu7251g,bu7251sg, bu7231g,bu7231sg, bu7252f/fvm,bu7252s f/fvm, bu7232f/fvm,bu7232s f/fvm description cmos comparator bu7251/bu7231family and bu7252/bu7232 family are input full swing and push pull output comparator. these ics integrate one op-amp or two independent op-amps and phase compensation capacitor on a single chip. the features of these ic s are low operating supply voltage that is +1.8v to 5.5v(single supply) and low supply current, extremely low input bias current. features 1) low operating supply voltage ( 1.8[v] 5.5[v]) 7) internal esd protection 2) 1.8 [v] 5.5[v](single supply) human bod y model (hbm) 4000[v](typ.) 0.9[v] 2.75[v](split supply) 8) wide temperature range 3) input and output full swing 40[ ] 85[ ] 4) push-pull output type (bu7251g,b u7252 family, bu7231g, bu7232 family) 5) high speed operation 40[ ] 105[ ] (bu7251 family, bu7252 family) (bu7251sg,bu7252s family, bu7231sg,bu7232s family) 6) low supply current (bu7231 family, bu7232 family) pin assignments 2007. october high speed single bu7251 g dual (bu7251sg:105 ) bu7252 f/fvm (bu7252s f/fvm:105 ) low pow er single bu7231 g dual (bu7231sg:105 ) bu7232 f/fvm (bu7232s f/fvm:105 ) 1 2 3 4 8 7 5 out1 in1- in1+ vss vdd out2 in2- in2+ ch1 - + ch2 + - 6 1 2 3 5 4 in- vss in+ vdd out sop8 ssop5 msop8 bu7252f bu7252sf bu7232f bu7232sf bu7252fvm bu7252sfvm bu7232fvm bu7232sfvm bu7251g bu7251sg bu7231g bu7231sg
2/16 absolute maximum ratings (ta=25[ ]) rating parameter symbol bu7251g bu7252 f/fvm bu7231g bu7232 f/fvm bu7251sg bu7252s f/fvm bu7231sg bu7232s f/fvm unit supply voltage vdd-vss 7 v differential input voltage (*1) vid vdd vss v input common-mode voltage range vicm (vss 0.3) to vdd 0.3 v operating temperature topr 40 to 85 40 to 105 storage temperature ts t g 55 to 125 maximum junction temperature tjmax 125 note: absolute maximum rating item indicates the condition which must not be exceeded. application of voltage in excess of absolute maximum rating or use out absoluted maximum rated temperature environment may c ause deterioration of characteristics. (*1) the voltage difference between inverting input and non-inverting input is the differential input voltage. then input terminal voltage is set to more then vee. electrical characteristics bu7251 family, bu7252 family (unless otherwise spec ified vdd=+3[v], vss=0[v], ta=25[ ]) guaranteed limit bu7251g bu7251sg bu7252 f/fvm bu7252s f/fvm parameter symbol temperature range min. typ. max. min. typ. max. unit condition input offset voltage (*2)(*4) vio 25 - 1 11 - 1 11 mv input offset current (*2) iio 25 - 1 - - 1 - pa input bias current (*2) ib 25 - 1 - - 1 - pa input common-mode voltage range vicm 25 0 - 3 0 - 3 v (vdd-vss)=3[v] large signal voltage gain av 25 - 90 - - 90 - db rl=10[k ? ] 25 - 15 35 - 35 65 supply current(*4) idd full range - - 50 - - 80 a rl= power supply rejection ratio psrr 25 - 80 - - 80 - db common-mode rejection ratio cmrr 25 - 80 - - 80 - db output source current (*3) ioh 25 1 2 - 1 2 - ma vdd-0.4 output sink current (*3) iol 25 3 6 - 3 6 - ma vss+0.4 high level output voltage (*4) voh 25 vdd-0.1 - - vdd-0.1 - - v rl=10[k ? ] low level output voltage (*4) vol 25 - - vss+0.1 - - vss+0.1 v rl=10[k ? ] output rise time tr 25 - 50 - - 50 - ns cl=15pf 100mv over drive output fall time tf 25 - 20 - - 20 - ns cl=15pf 100mv over drive propagation delay l to h tplh 25 - 0.55 - - 0.55 - s cl=15pf 100mv over drive propagation delay h to l tphl 25 - 0.25 - - 0.25 - s cl=15pf 100mv over drive (*2) abusolute values (*3) reference to power dissipation under the high temperature environment and decide the output current. continuous short circuit is occurring the degenerate of output current characteristics. (*4) full range bu7251,bu7252 ta =-4 0 [ ] to +85[ ] bu7251s,bu7252s ta =-4 0[ ] to +105[ ] electrical characteristics bu7231 family, bu7232 family (unless otherwise spec ified vdd=+3[v], vss=0[v], ta=25[ ]) guaranteed limit bu7231g bu7231sg bu7232f/fvm bu7232s f/fvm parameter symbol temperature range min. min. typ. max. unit condition input offset voltage (*5) vio 25 - 1 11 - 1 11 mv input offset current (*5) iio 25 - 1 - - 1 - pa input bias current (*5) ib 25 - 1 - - 1 - pa input common-mode voltage range vicm 25 0 - 3 0 - 3 v (vdd-vss)=3[v] large signal voltage gain av 25 - 90 - - 90 - db rl=10[k ? ] 25 - 5 15 - 10 25 supply current idd full range - - 30 - - 50 a rl= power supply rejection ratio psrr 25 - 80 - - 80 - db common-mode rejection ratio cmrr 25 - 80 - - 80 - db output source current (*6) ioh 25 1 2 - 1 2 - ma vdd-0.4 output sink current (*6) iol 25 3 6 - 3 6 - ma vss+0.4 high level output voltage (*7) voh 25 vdd-0.1 - - vdd-0.1 - - v rl=10[k ? ] low level output voltage (*7) vol 25 - - vss+0.1 - - vss+0.1 v rl=10[k ? ] output rise time tr 25 - 50 - - 50 - ns cl=15pf 100mv over drive output fall time tf 25 - 20 - - 20 - ns cl=15pf 100mv over drive propagation delay l to h tplh 25 - 1.7 - - 1.7 - s cl=15pf 100mv over drive propagation delay h to l tphl 25 - 0.5 - - 0.5 - s cl=15pf 100mv over drive (*5) abusolute values (*6) reference to power dissipation under the high temperature environment and decide the output current. continuous short circuit is occurring the degenerate of output current characteristics. (*7) full range bu7231,bu7232 ta = - 4 0 [ ] to +85[ ] bu7231s,bu7232s ta = - 4 0 [ ] to +105[ ]
3/16 0 10 20 30 40 50 -60 -30 0 30 60 90 120 am bient tem perature [ ] supply current [a] example of electrical characteristics bu7251 family (*) the above date is ability value of sa mple, it is not guaranteed. bu7251g 40[ ] to 85[ ] bu7251sg 40[ ] to 105[ ] 0 2 4 6 8 10 0.0 0.5 1.0 1.5 2.0 2.5 3.0 output voltage [v] output source current [ma] 0 10 20 30 40 50 60 123456 supply voltage [v] supply current [a] fig.3 supply current ? supply voltage 25 -40 85 105 bu7251 family 0 200 400 600 800 050100150 ambient temperature [ ] power dissipation [mw ] . bu7251sg bu7251 family fig.2 derating curve 1.8v 5.5v 3.0v fig.4 supply current ? ambient temperature bu7251 family 0 2 4 6 123456 supply voltage [v] output voltage high [v] -40 25 85 105 fig.5 output voltage high ? supply voltage (rl=10[k ? ]) bu7251 family 0 2 4 6 8 -60 -30 0 30 60 90 120 ambient temperature [ ] output voltage high [v] 1.8v 5.5v 3.0v fig.6 output voltage high ? ambient temperature (rl=10[k ? ]) bu7251 family 0 1 2 3 4 5 -60 -30 0 30 60 90 120 ambient temperature [ ] output source current [ma] 1.8v 5.5v 3.0v fig.10 output source current ? ambient temperature (vout=vdd-0.4[v]) bu7251 family 0 10 20 30 40 50 - 60 - 30 0 30 60 90 120 ambient temperature [ ] output voltage low [mv] fig.8 output voltage low ? ambient temperature (rl=10[k ? ]) 1.8v 5.5v 3.0v bu7251 family -40 25 85 105 fig.9 output source current ? supply voltage (vdd=3[v]) bu7251 family 0 5 10 15 20 25 30 0.0 0.5 1.0 1.5 2.0 2.5 3.0 output voltage [v] output sink current [ma] -40 25 85 105 bu7251 family fig.11 output sink current ? output voltage (vdd=3[v]) 0 5 10 15 20 -60-300 306090120 ambient temperature [ ] output sink current [ma] 5.5v 1.8v 3.0v bu7251 family fig.12 output sink current ? ambient temperature (vout=vss+0.4[v]) 0 10 20 30 40 50 123456 supply voltage [v] output voltage low [mv] -40 25 85 105 bu7251 family fig.7 output voltage low ? supply voltage (rl=10[k ? ]) 0 200 400 600 800 0 50 100 150 ambient temperature [ ] power dissipation [mw] . bu7251g bu7251 family fig.1 derating curve
4/16 60 80 100 120 140 160 -60 -30 0 30 60 90 120 ambient temperature [ ] large signal voltage gain [db] bu7251 family (*) the above date is ability value of sa mple, it is not guaranteed. bu7251g 40[ ] to 85[ ] bu7251sg 40[ ] to 105[ ] -10.0 -7.5 -5.0 -2.5 0.0 2.5 5.0 7.5 10.0 123456 supply voltage [v] input offset voltage [mv] -40 25 85 105 bu7251 family fig.13 input offset voltage ? supply voltage (vicm=vdd, vout=0.1[v]) 60 80 100 120 140 160 123456 supply voltage [v] large signal voltage gain [db] -40 25 85 105 bu7251 family fig.16 large signal voltage gain ? supply voltage -10.0 -7.5 -5.0 -2.5 0.0 2.5 5.0 7.5 10.0 -60 -30 0 30 60 90 120 ambient temperature [ ] input offset voltage [mv] 5.5v 1.8v 3.0v bu7251 family fig.14 input offset voltage ? ambient temperature (vicm=vdd, vout=0.1[v]) -15 -10 -5 0 5 10 15 -1 0 1 2 3 4 input voltage [v] input offset voltage [mv] -40 25 85 105 fig.15 input offset voltage ? input voltage (vdd=3[v]) bu7251 family 3.0v 5.5v 1.8v fig.17 large signal voltage gain ? ambient temperature bu7251 family 0 20 40 60 80 100 120 123456 supply voltage [v] common mode rejection ratio [db] -40 25 85 105 fig.18 common mode rejection ratio ? supply voltage (vdd=3[v]) bu7251 family 0 20 40 60 80 100 120 -60 -30 0 30 60 90 120 ambient temperature [ ] power supply rejection ratio [db] fig.20 power supply rejection ? ambient temperature bu7251 family 0 20 40 60 80 100 120 -60 -30 0 30 60 90 120 ambient temperature [ ] common mode rejection ratio [db] 5.5v 1.8v 3.0v bu7251 family fig.19 common mode rejection ratio ? ambient temperature (vdd=3[v]) 0.0 0.5 1.0 1.5 2.0 -60 -30 0 30 60 90 120 ambient temperature [ ] propagation delay l-h [s] 5.5v 1.8v 3.0v fig.21 propagation delay l-h ? ambient temperature bu7251 family 0.0 0.2 0.4 0.6 0.8 -60 -30 0 30 60 90 120 ambient temperature [ ] propagation delay h-l [s] 5.5v 1.8v 3.0v bu7251 family fig.22 propagation delay h-l ? ambient temperature
5/16 bu7252 family (*) the above date is ability value of samp le, it is not guaranteed. bu7252 f/fvm 40[ ] to 85[ ] bu7252s f/fvm 40[ ] to 105[ ] 0 200 400 600 800 1000 0 50 100 150 ambient temperature [ ] . power dissipation [mv] bu7252f bu7252 family fig.1 derating curve bu7252fvm 0 50 100 150 123456 supply voltage [v] supply current [a] 85 -40 25 105 bu7252 family fig.3 supply current ? supply voltage 0 50 100 150 -60 -30 0 30 60 90 120 ambient temperature [ ] supply current [a] 3.0v 1.8v 5.5v fig.4 supply curreny ? ambient temperature bu7252 family 0 10 20 30 40 50 123456 supply voltage [v] output voltage low [mv] 85 105 -40 25 fig.7 output voltage low ? supply voltage (rl=10[k ? ]) bu7252 family 0 10 20 30 40 50 -60-30 0 306090120 ambient temperature [ ] output voltage low [mv] 1.8v 5.5v 3.0v fig.8 output voltage low ? ambient temperature (rl=10[k ? ]) bu7252 family 0 5 10 15 20 25 30 0.0 0.5 1.0 1.5 2.0 2.5 3.0 output voltage [v] output sink current [ma] -40 25 85 105 bu7252 family fig.11 output sink current ? output voltage (vdd=3[v]) 0 5 10 15 20 -60-300 306090120 ambient temperature [ ] output sink current [ma] 5.5v 1.8v 3.0v fig.12 output sink current ? ambient temperature (vout=vss+0.4[v]) bu7252 family 0 200 400 600 800 1000 0 50 100 150 ambient temperature [ ] . power dissipation [mv] bu7252sf bu7252 family fig.2 derating curve bu7252sfvm 0 2 4 6 8 -60 -30 0 30 60 90 120 ambient temperature [ ] output voltage high [v] 1.8v 5.5v 3.0v fig.6 output voltage high ? ambient temperature (rl=10[k ? ]) bu7252 family 0 1 2 3 4 5 -60 -30 0 30 60 90 120 ambient temperature [ ] output source current [ma] 1.8v 5.5v 3.0v fig.10 output source current ? a mbient tem p erature bu7252 family 0 2 4 6 8 10 0 0.5 1 1.5 2 2.5 3 output voltage [v] output source current [ma] -40 25 85 105 fig.9 output source current ? output voltage vdd=3[v]) bu7252 family 0 2 4 6 8 123456 supply voltage [v] output voltage high [v] -40 25 85 105 fig.5 output voltage high ? supply voltage (rl=10[k ? ]) bu7252 family 85 105
6/16 20 40 60 80 100 120 140 160 -60-30 0 306090120 ambient temperature [ ] large signal voltage gain [db] bu7252 family (*) the above date is ability value of samp le, it is not guaranteed. bu7252 f/fvm 40[ ] to 85[ ] bu7252s f/fvm 40[ ] to 105[ ] 0.0 0.5 1.0 1.5 2.0 -60 -30 0 30 60 90 120 ambient temperature [ ] propagation delay l-h [s] 5.5v 1.8v 3.0v fig.21 propagation delay l-h ? ambient temperature bu7252 family -10.0 -7.5 -5.0 -2.5 0.0 2.5 5.0 7.5 10.0 -60 -30 0 30 60 90 120 ambient temperature [ ] input offset voltage [mv] 5.5v 1.8v 3.0v bu7252 family fig.14 input offset voltage ? ambient temperature (vicm=vdd,vout=0.1[v]) -15 -10 -5 0 5 10 15 -1 0 1 2 3 4 input voltage [v] input offset voltage [mv] -40 25 105 fig.15 input offset voltage ? input voltage (vdd=3[v]) bu7252 family 0 20 40 60 80 100 120 123456 supply voltage [v] common mode rejection ratio [db] -40 25 105 fig.18 common mode rejection ratio ? supply voltage (vdd=3[v]) bu7252 family 0 20 40 60 80 100 120 -60 -30 0 30 60 90 120 ambient temperature [ ] common mode rejection ratio [db] 5.5v 1.8v 3.0v bu7252 family fig.19 common mode rejection ? ambient temperature (vdd=3[v]) fig.20 power supply rejection ratio ? ambient 0 20 40 60 80 100 120 -60 -30 0 30 60 90 120 ambient temperature [ ] power supply rejection ratio [db] bu7252 family 0.0 0.2 0.4 0.6 0.8 -60 -30 0 30 60 90 120 ambient temperature [ ] propagation delay h-l [s] 5.5v 1.8v 3.0v fig.22 propagation delay h-l ? ambient temperature bu7251 family 5.5v 1.8v 3.0v fig.17 large signal voltage gain ? ambient temperatur e bu7252 family 20 40 60 80 100 120 140 160 123456 supply voltage [v] large signal voltage gain [db] 25 85 105 bu7252 family fig.16 large signal voltage gain ? supply voltage -40 -10.0 -7.5 -5.0 -2.5 0.0 2.5 5.0 7.5 10.0 123456 supply voltage[v] input offset voltage [mv] -40 25 105 bu7252 family fig.13 input offset voltage ? supply voltage (vicm=vdd,vout=0.1[v]) 8 5 85 85
7/16 2 4 6 8 10 12 -60 -30 0 30 60 90 120 am bient tem perature [ ] supply current [a] bu7231 series (*) the above date is ability value of sa mple, it is not guaranteed. bu7231g 40[ ] to 85[ ] bu7231sg 40[ ] to 105[ ] fig.6 output voltage high ? ambient temperature (rl=10[k ? ]) 0 10 20 30 40 50 02468 supply voltage [v] output voltage low [mv] 0 4 8 12 16 20 123456 supply voltage [v] supply current [a] fig.3 supply current ? supply voltage -40 25 85 105 bu7231 family 0 200 400 600 800 050100150 ambient temperature [ ] power dissipation [mw ] . bu7231sg bu7231 family fig.2 derating curve 1.8v 5.5v 3.0v fig.4 supply current ? ambient temperature bu7231 family 0 10 20 30 40 50 - 60 -30 0 30 60 90 120 ambient temperature [ ] output voltage low [mv] fig.8 output voltage low ? ambient temperature (rl=10[k ? ]) 1.8v 5.5v 3.0v bu7231 family 0 1 2 3 4 5 -60 -30 0 30 60 90 120 ambient temperature [ ] output source current [ma] 1.8v 5.5v 3.0v fig.10 output source current ? ambient temperature (vout=vdd-0.4[v]) bu7231 family 0 5 10 15 20 25 30 0.0 0.5 1.0 1.5 2.0 2.5 3.0 output voltage [v] output sink current [ma] -40 25 85 105 bu7231 family fig.11 output sink current ? output voltage (vdd=3[v]) 0 5 10 15 20 -60 -30 0 30 60 90 120 ambient temperature [ ] output sink current [ma] 5.5v 1.8v 3.0v bu7231 family fig.12 output sink current ? ambient temperature (vout=vss+0.4[v]) bu7231 family -40 25 85 105 fig.7 output voltage low ? supply voltage (rl=10[k ? ]) 0 2 4 6 123456 supply voltage [v] output voltage high [v] bu7231 family -40 25 85 105 fig.5 output voltage ? supply voltage (rl=10[k ? ]) 0 200 400 600 800 0 50 100 150 ambient temperature [ ] power dissipation [mw] . bu7231g bu7231 family fig.1 derating curve 0 2 4 6 8 10 0 0.5 1 1.5 2 2.5 3 output voltage [v] output source current [ma] fig.9 output source current ? output voltage (vdd=3[v]) bu7231 family -40 25 85 105 0 2 4 6 8 -60 -30 0 30 60 90 120 ambient temperature [ ] output voltage high [v] bu7231 family 5.5v 3.0v 1.8v 85 105
8/16 60 80 100 120 140 160 -60-30 0 306090120 ambient temperature [ ] large signal voltage gain [db] bu7231 series (*) the above date is ability value of sa mple, it is not guaranteed. bu7231g 40[ ] to 85[ ] bu7231sg 40[ ] to 105[ ] -10.0 -7.5 -5.0 -2.5 0.0 2.5 5.0 7.5 10.0 123456 supply voltage [v] input offset voltage [mv] -40 25 85 105 bu7231 family fig.13 input offset voltage ? supply voltage (vicm=vdd, vout=0.1[v]) 0 1 2 3 4 5 -60 -30 0 30 60 90 120 ambient temperature [ ] propagation delay l-h [s] 5.5v 1.8v 3.0v fig.21 propagation delay l-h ? ambient temperature bu7231 family 0.0 0.3 0.6 0.9 1.2 1.5 -60 -30 0 30 60 90 120 ambient temperature [ ] propagation delay h-l [s] 5.5v 1.8v 3.0v bu7231 family fig.22 propagation delay h-l ? ambient temperature 60 80 100 120 140 160 123456 supply voltage [v] large signal voltage gain [db] -40 25 85 105 bu7231 family fig.16 large signal voltage gain ? supply voltage 0 20 40 60 80 100 120 -60 -30 0 30 60 90 120 ambient temperature [ ] power supply rejection ratio [db] bu7231 family fig.20 power supply rejection ratio ? ambient temperature 0 20 40 60 80 100 120 123456 supply voltage [v] common mode rejection ratio [db] -40 25 85 105 bu7231 family fig.18 common mode rejection ratio ? supply voltage (vdd=3[v]) -15 -10 -5 0 5 10 15 -101234 input voltage [v] input offset voltage [mv] -40 25 85 105 bu7231 family fig.15 input offset voltage ? input voltage (vdd=3[v]) 3.0v 5.5v 1.8v bu7231 family fig.17 large signal voltage gain ? ambient temperature 0 20 40 60 80 100 120 -60 -30 0 30 60 90 120 ambient temperature [ ] common mode rejection ratio [db] 5.5v 1.8v 3.0v bu7231 family fig.19 common mode rejection ratio ? ambient temperature (vdd=3[v]) -10.0 -7.5 -5.0 -2.5 0.0 2.5 5.0 7.5 10.0 -60 -30 0 30 60 90 120 ambient temperature [ ] input offset voltage [mv] bu7231 family 5.5v 1.8v 3.0v fig.14 input offset voltage ? ambient temperature (vicm=vdd, vout=0.1[v])
9/16 bu7232 family (*) the above date is ability value of samp le, it is not guaranteed. bu7232 f/fvm 40[ ] to 85[ ] bu7232s f/fvm 40[ ] to 105[ ] 0 200 400 600 800 1000 0 50 100 150 ambient temperature [ ] . power dissipation [mv] 0 200 400 600 800 1000 0 50 100 150 ambient temperature [ ] . power dissipation [mv] 0 10 20 30 40 50 -60-30 0 306090120 ambient temperature [ ] supply current [a] 3.0v 1.8v 5.5v fig.4 supply current ? a mbient temperature bu7232 family 0 10 20 30 40 50 1234567 supply voltage [v] output voltage low [mv] 85 105 -40 25 fig.7 output voltage low ? supply voltage (rl=10[k ? ]) bu7232 family 0 2 4 6 8 1234567 supply voltage [v] output voltage high [v] -40 25 85 105 fig.5 output voltage high ? supply voltage (rl=10[k ? ]) bu7232 family 0 10 20 30 40 50 -60 -30 0 30 60 90 120 ambient temperature [ ] output voltage low [mv] 1.8v 5.5v 3.0v fig.8 output voltage low ? ambient temperature (rl=10[k ? ]) bu7232 family 0 10 20 30 0.0 0.5 1.0 1.5 2.0 2.5 3.0 output voltage [v] output sink current [ma] -40 25 85 105 bu7232 family fig.11 output sink current ? output voltage (vdd=3[v]) 0 5 10 15 20 -60 -30 0 30 60 90 120 ambient temperature [ ] output sink current [ma] 5.5v 1.8v 3.0v fig.12 output sink current ? ambient temperature (vout=vss+0.4[v]) bu7232 family 0 1 2 3 4 5 -60 -30 0 30 60 90 120 ambient temperature [ ] output source current [ma] 1.8v 5.5v 3.0v fig.10 output source current ? ambient temperature (vout=vdd-0.4[v]) bu7232 family 0 2 4 6 8 10 0 0.5 1 1.5 2 2.5 3 output voltage [v] output source current [ma] -40 25 85 105 fig.9 output source current ? output volta g e bu7232 family 0 2 4 6 8 -60 -30 0 30 60 90 120 ambient temperature [ ] output voltage high [v] 1.5v 5.5v 3.0v fig.6 output voltage ? ambient temperature (rl=10[k ? ]) bu7232 family 0 10 20 30 40 50 123456 supply voltage [v] supply current [a] 85 -40 25 105 bu7232 family fig.3 supply current ? supply voltage bu7232f bu7232 family fig.1 derating curve bu7232fvm 85 bu7232sf bu7232 family fig.2 derating curve bu7232sfvm 105
10/16 60 80 100 120 140 160 -60-30 0 306090120 ambient temperature [ ] large signal voltage gain [db] bu7232 family (*) the above date is ability value of samp le, it is not guaranteed. bu7232 f/fvm 40[ ] to 85[ ] bu7232s f/fvm 40[ ] to 105[ ] -15 -10 -5 0 5 10 15 -101234 input voltage [v] input offset voltage [mv] 0.0 0.3 0.6 0.9 1.2 1.5 -60 -30 0 30 60 90 120 ambient temperature [ ] propagation delay h-l [us] fig.17 large signal voltage gain ? a mbient tem p erature -10.0 -7.5 -5.0 -2.5 0.0 2.5 5.0 7.5 10.0 123456 ambient temperature [ ] input offset voltage [mv] -40 25 105 bu7232 family fig.13 input offset voltage ? ambient temperature (vicm=vdd, vout=0.1[v]) fig.15 input offset voltage ? input voltage (vdd=3[v]) bu7232 family 5.5v 3.0v bu7232 family 0 20 40 60 80 100 120 123456 supply voltage [v] common mode rejection ratio [db] -40 25 105 fig.18 common mode rejection ratio ? supply voltage (vdd=3[v]) bu7232 family fig.20 power supply rejection ratio ? ambient temperature 0 20 40 60 80 100 120 -60 -30 0 30 60 90 120 ambient temperature [ ] power supply rejection ratio [db] bu7232 family 0 20 40 60 80 100 120 -60 -30 0 30 60 90 120 ambient temperature [ ] common mode rejection ratio [db] 5.5v 1.8v 3.0v bu7232 family fig.19 common mode rejection ratio ? ambient temperature (vdd=3[v]) 60 80 100 120 140 160 123456 supply voltage [v] large signal voltage gain [db] 25 -40 105 bu7232 family fig.16 large signal voltage gain ? supply voltage 85 fig.22 propagation delay h-l ? ambient temperature 5.5v 1.8v 3.0v bu7232 family fig.21 propagation delay l-h ? ambient temperature 0 1 2 3 4 5 -60 -30 0 30 60 90 120 ambient temperature [ ] propagation delay l-h [s] 5.5v 1.8v 3.0v bu7232 family -10.0 -7.5 -5.0 -2.5 0.0 2.5 5.0 7.5 10.0 -60 -30 0 30 60 90 120 ambient temperature [ ] input offset voltage [mv] 5.5v 1.8v 3.0v bu7232 family fig.14 input offset voltage ? ambient temperature (vicm=vdd, vout=0.1[v]) 1.8v -40 25 105 85 85
11/16 schematic diagram test circuit1 null method vdd,vss,ek,vicm, unit : [v] parameter vf s1 s2 s3 vdd vss ek vicm calculation input offset voltage vf1 on on off 3 0 -0.1 0.3 1 vf2 -0.3 large signal voltage gain vf3 on on on 3 0 -2.7 0.3 2 vf4 0 common-mode rejection ratio (input common-mode voltage range) vf5 on on off 3 0 -0.1 3 3 vf6 1.8 power supply rejection ratio vf7 on on off 5.5 0 -0.1 0.3 4 calculation 1. input offset voltage (vio) 2. large signal voltage gain (av) 3. common-mode rejection ratio (cmrr) 4. power supply rejection ratio (psrr) vd d rf 50[k ? ] s1 ri 1[m ? ] rs 50[ ? ] s2 rl s3 500[k ? ] 500[k ? ] 0.01[f] r k e k r k +15[v ] -15[v] null v f dut vss ri 1[m ? ] rs 50[ ? ] 50[k ? ] vic m 0.47[f] 0.1[uf] 0.1[uf] fig.2 test circuit 1 (one channel only) vio = |vf1| 1+rf/rs [v] fig.1 simplified schematic
12/16 test circuit2 switch condition unit : [v] sw no. sw 1 sw 2 sw 3 sw 4 sw 5 sw 6 sw 7 sw 8 supply current off on on off off off off off maximum output voltage rl=10 [k ? ] off on on on off off on off output current off off off off off on off off response time on off on off on off off on v in [v] t 100mv over drive 1.6[v] 1.4[v] vre f=1 .5 [v] v out [v] tplh t 3[v] 0[v] 1.5[v] v in [v] 100mv over drive 1.6[v] 1.4[v] vref=1.5[v] 3[v] 0[v] v out [v] tphl t 1.5[v] input wave input wave output wave output wave sw1 sw2 sw 5 sw 6 sw 7 sw 4 sw 3 c l sw 8 r l gnd vdd=3[v] v o vin- vin+ fig4. slew rate fig3. test circuit2 (one channel only)
13/16 description of electrical characteristics described here are the terms of electric characteristics used in this technical note. items and symbols used are also shown. note that item name and symbol and their meaning may differ from those on another manufacture ?s document or general document . 1. absolute maximum ratings absolute maximum rating item indicates the condition which must not be exceeded. application of voltage in excess of absolute maximum rating or use out of absolute maximum rated temper ature environment may cause deter ioration of characteristics. 1.1 power supply voltage vdd/vss indicates the maximum voltage that can be applied between the posit ive power supply terminal and negative power supply terminal without deterioration or destruction of characteristics of internal circuit. 1.2 differential input voltage vid indicates the maximum voltage that can be applied between non-invert ing terminal and inverting terminal without deterioration a nd destruction of characteristics of ic. 1.3 input common-mode voltage range vicm indicates the maximum voltage that can be applied to non-inverti ng terminal and inverting terminal without deterioration or des truction of characteristics. input common-mode voltage range of the maxi mum ratings not assure normal operation of ic. when normal operation of ic is desired, the input common-mode vo ltage of characteristics item must be followed. 1.4 power dissipation pd indicates the power that can be consumed by sp ecified mounted board at the ambient temperature 25 (normal temperature). as for package product, pd is determined by the temperature that can be permitted by ic chip in the package maximum junction temperature and thermal resistance of the package 2. electrical characteristics item 2.1 input offset voltage vio indicates the voltage difference between non-inverting terminal and inverting terminal. it can be translated into the input v oltage difference required for setting the output voltage at 0 [v] 2.2 input offset current iio indicates the difference of input bias current between non-inverting terminal and inverting terminal. 2.3 input bias current ib indicates the current that flows into or out of the input te rminal. it is defined by the average of input bias current at non -inverting terminal and input bias current at inverting terminal. 2.4 input common-mode voltage range vicm indicates the input voltage range where ic operates normally. 2.5 large signal voltage gain av indicates the amplifying rate (gain) of output voltage agai nst the voltage difference between non-inverting terminal and inve rting terminal. it is normally the amplifying rate (gain) with reference to dc voltage. av = (output voltage fluctuation) / (input offset fluctuation) 2.6 circuit current icc indicates the ic current that flows under specified conditions and no-load steady status. 2.7 output sink current ol indicates the maximum current that can be output under specif ied output condition (such as output voltage and load condition). 2.8 output saturation voltage, low level output voltage vol indicates the voltage range that can be output under specif ied load conditions. 2.9 output leakage current, high level output current i leak indicates the current that flows into ic under specified input and output conditions. 2.10 response time tre the interval between the applicat ion of an input and output condition. 2.11 common-mode rejection ratio cmrr indicates the ratio of fluctuation of input offset voltage when in-phase input voltage is changed. it is normally the fluctua tion of dc. cmrr change of input common-mode voltage / input offset fluctuation 2.12 power supply rejection ratio psrr indicates the ratio of fluctuation of input offset volt age when supply voltage is changed. it is normally the fluctuation of dc. psrr change of power supply voltage / input offset fluctuation
14/16 derating curve power dissipation (total loss) indicates the power that can be consumed by ic at ta=25 (normal temperature).ic is heated when it consumed power, and the temperat ure of ic ship becomes higher than ambient temperature. the temperature that can be accepted by ic chip depends on circuit configuration, manufacturing process, and cons umable power is limited. power dissipation is determined by the temperature allowed in ic ch ip (maximum junction temperature) and thermal resistance of package (heat dissipation capability). the maximum junction temperature is typically equal to the maximum value in the storage package (heat dissipation capability). the maximum junction temperature is typically equal to the maximum value in the storage temperature range. h eat generated by consumed power of ic radiates from the mold resin or lead frame of the package. the parameter which indicates this heat dissipation capability (hardness of heat release) is called thermal resistance, represented by the symbol j-a[ /w]. the temperature of ic inside the package can be estimated by this thermal resistance. fig.6 (a) shows the model of therma l resistance of the package. thermal resistance ja, ambient temperature ta, junction temperature tj, and power dissipation pd can be calculated by the equation below : ja (tj ta) / pd [ /w] ????? derating curve in fig.6 (b) indicates power that can be consumed by ic with reference to ambient temperature. power that can be consumed by ic begins to attenuate at certain ambien t temperature. this gradient is determined by thermal resistance ja. thermal resistance ja depends on chip size, power consumption, package, ambient temperature, package condition, wind velocity, etc even when the same of package is used. thermal reduction curve indicates a reference value measured at a specifi ed condition. fig7(c)-(f) show a der ating curve for an example of bu 7251family, bu7252 family, bu7231 family, bu7232 family. *8 *9 *10 unit 5.4 6.2 4.8 [mw/ ] when using the unit above ta=25[ ], subtract the value above per degree[ ]. permissible dissipation is the value when fr4 glass epoxy board 70[mm] 70[mm] 1.6[mm] (cooper foil area below 3[ ]) is mounted. 05075100125 150 25 p1 p2 pd(max) lsi M [w] ja2 ja1 tj(max) ja2 < ja1 ?? ta[ ] bu7251/bu7231 tj(max) power dissipation pd:[w] a mbient temper ature:ta [ ] (a) thermal resistance (b) derating curve fig6. thermal resistance and power dissipation fig7. derating curve 0 200 400 600 800 050100150 ambient temperature [ ] power dissipation [mw ] . 85 0 200 400 600 800 1000 0 50 100 150 ambient temperature [ ] power dissipation [mw] . 85 0 200 400 600 800 0 50 100 150 ambient temperature [ ] power dissipation [mw ] . bu7231sg(*8) 105 0 200 400 600 800 1000 0 50 100 150 ambient temperature [ ] power dissipation [mw] . 105 (c) bu7251g bu7231g (d) bu7252f/fvm bu7232f/fvm (e) bu7251sg bu7231sg (f) bu7252s f/fvm bu72432s f/fvm bu7251sg(*8) bu7251g(*8) bu7231g(*8) 540[mw] 620[mw] 480[mw] 540[mw] bu7252f(*9) bu7232f(*9) bu7252fvm(*10) bu7232fvm(*10) 620[mw] 480[mw] bu7252sf(*9) bu7232sf(*9) bu7252sfvm(*10) bu7232sfvm(*10) a mbient temperatur e ta [ ] chip sur face temperatur e tj [ ] power dissipation p [w] ja = ( tj ` ta ) / pd [ /w]
15/16 cautions on use 1) absolute maximum ratings absolute maximum ratings are the values which indicate the limits, within which the given voltage range can be safely charged to the terminal. however, it does not guar antee the circuit operation. 2) applied voltage to the input terminal for normal circuit operation of voltage comparator, please input voltage for its input terminal within input common mode voltage vdd+0.3[v]. then, regardless of power supply volt age,vss-0.3[v] can be applied to input terminals without deterioration or des truction of its characteristics. 3) operating power supply (split power supply/single power supply) the voltage comparator operates if a given level of voltage is applied between vdd and vss. therefore, the op erational amp lifier can be operated under single power supply or split power supply. 4) power dissipation (pd) if the ic is used under excessive power dissipation. an increase in the chip temperature will cause deterioration of the radical characteristics of ic. for example, reduction of current capability. take c onsideration of the effective power dissipation and thermal design with a sufficient margin. pd is re ference to the provided power dissipation curve. 5) short circuits between pins and incorrect mounting short circuits between pins and incorrect mounting when mounting the ic on a printed circuits board, take notice of the directi on and positioning of the ic. if ic is mounted erroneously, it may be damaged. also, when a foreign object is inserted between output, between output and vdd terminal or vss termina l which causes short circuit, the ic may be damaged. 6) using under strong electromagnetic field be careful when using the ic under strong elec tromagnetic field because it may malfunction. 7) usage of ic when stress is applied to the ic through warp of the printed circuit board, the characteristics may fluctuate due to the piezo effect. be careful of the warp of the printed circuit board. 8) testing ic on the set board when testing ic on the set board, in cases where t he capacitor is connected to the low impedance, make sure to discharge per fabrication because there is a possibility that ic may be damaged by stress. when removing ic from the set board, it is essential to cut supply voltage. as a countermeasure against the stat ic electricity, observe proper groun ding during fabrication process and take due care when carrying and storage it. 9) the ic destruction caused by capacitive load the transistors in circuits may be damaged when vdd terminal and vss terminal is shorted with the charged output terminal capacitor.when ic is used as a o perational amplifier or as an application circuit, where oscillation is not activated by an output c apacitor,the output capacito r must be kept below 0.1[ f] in order to prevent the damage mentioned above. 10) decupling capacitor insert the deculing capacitance between vdd and vss , for stable operation of operational amplifier. 11) latch up be careful of input vltage that exceed the vdd and vss. when cmos device have sometimes occur latch up operation. and protect the ic from abnormaly noise
16/16 dimensions model number construction packing specification reference ssop5 sop8 msop8 packing specification name ssop5 tr 3000 sop8 e2 2500 msop8 tr 3000 package quantity embossed carrier tape reel direction of feed 1pin 1234 1234 1234 1234 1234 1234 1234 reel direction of feed 1pin 1234 1234 1234 1234 1234 1234 1234 reel 1pin x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x direction of feed reel direction of feed 1pin x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x e2 embossed tape on reel with pin 1 near far when pulled out tr embossed tape on reel with pin 1 near far when pulled out rohm package type ? g : ssop5 ? f : sop8 ? fvm : msop8 ? bu7251 bu7251s ? bu7231 bu7231s ? bu7252 bu7252s ? bu7232 bu7232s ? specify the product by the model number when placing an order. ? make sure of the combinations of items. ? start with the leftmost space without leaving any empty space between characters. b u 7 2 5 2 s f - e 2
notes no technical content pages of this document may be reproduced in any form or transmitted by any means without prior permission of rohm co.,ltd. the contents described herein are subject to change without notice. the specifications for the product described in this document are for reference only. upon actual use, therefore, please request that specifications to be separately delivered. application circuit diagrams and circuit constants contained herein are shown as examples of standard use and operation. please pay careful attention to the peripheral conditions when designing circuits and deciding upon circuit constants in the set. any data, including, but not limited to application circuit diagrams information, described herein are intended only as illustrations of such devices and not as the specifications for such devices. rohm co.,ltd. disclaims any warranty that any use of such devices shall be free from infringement of any third party's intellectual property rights or other proprietary rights, and further, assumes no liability of whatsoever nature in the event of any such infringement, or arising from or connected with or related to the use of such devices. upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or otherwise dispose of the same, no express or implied right or license to practice or commercially exploit any intellectual property rights or other proprietary rights owned or controlled by rohm co., ltd. is granted to any such buyer. products listed in this document are no antiradiation design. appendix1-rev2.0 thank you for your accessing to rohm product informations. more detail product informations and catalogs are available, please contact your nearest sales office. rohm customer support system the americas / eupope / asia / japan contact us : webmaster@ rohm.co. jp www.rohm.com copyright ? 2007 rohm co.,ltd. the products listed in this document are designed to be used with ordinary electronic equipment or de vices (such as audio visual equipment, office-automation equipment, communications devices, electrical appliances and electronic toys). should you intend to use these products with equipment or devices which require an extremely high level of reliability and the malfunction of which would directly endanger human life (such as medical instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers and other safety devices), please be sure to consult with our sales representative in advance. it is our top priority to supply products with the utmost quality and reliability. however, there is always a chance of failure due to unexpected factors. therefore, please take into account the derating characteristics and allow for sufficient safety features, such as extra margin, anti-flammability, and fail-safe measures when designing in order to prevent possible accidents that may result in bodily harm or fire caused by component failure. rohm cannot be held responsible for any damages arising from the use of the products under conditions out of the range of the specifications or due to non-compliance with the notes specified in this catalog. 21, saiin mizosaki- cho, ukyo-ku, kyoto 615-8585, japan tel : +81-75-311-2121 fax : +81-75-315-0172 appendix

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